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authorTimothy Pearson <kb9vqf@pearsoncomputing.net>2013-10-30 13:12:43 -0500
committerTimothy Pearson <kb9vqf@pearsoncomputing.net>2013-10-30 13:12:43 -0500
commitf27e0f01840bcc42e521beb29b4f5964b1649bda (patch)
tree01011ca0cc9b0c5f66d3e6c4e1e1410220065cc8 /clients/tde/src/part/fpgaview/part.h
parent8faa3da1094d1785d3343c2869d9f8c95f01cf97 (diff)
downloadulab-f27e0f01840bcc42e521beb29b4f5964b1649bda.tar.gz
ulab-f27e0f01840bcc42e521beb29b4f5964b1649bda.zip
Allow data processing RAM size to be configured by changing a Verilog parameter on the FPGA side
Diffstat (limited to 'clients/tde/src/part/fpgaview/part.h')
-rw-r--r--clients/tde/src/part/fpgaview/part.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/clients/tde/src/part/fpgaview/part.h b/clients/tde/src/part/fpgaview/part.h
index 81f74f7..8262689 100644
--- a/clients/tde/src/part/fpgaview/part.h
+++ b/clients/tde/src/part/fpgaview/part.h
@@ -250,7 +250,10 @@ namespace RemoteLab
TQImage m_dataInputImage;
TQFile* m_dataOutputFile;
TQByteArray m_dataByteArray;
- int m_dataMemorySize;
+ unsigned int m_dataMemorySize;
+ unsigned int m_dataMemorySizePrev;
+ unsigned int m_dataMemoryImageWidth;
+ unsigned int m_dataMemoryImageHeight;
ImageViewerWindow* m_inputImageViewer;
ImageViewerWindow* m_outputImageViewer;