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| author | Timothy Pearson <kb9vqf@pearsoncomputing.net> | 2014-01-12 15:59:45 -0600 |
|---|---|---|
| committer | Timothy Pearson <kb9vqf@pearsoncomputing.net> | 2014-01-12 15:59:45 -0600 |
| commit | 061289c61346568047e75a15f4ab1b874e4654d1 (patch) | |
| tree | 5b6e5fc0e84bf365f0735178680796ebc2593567 /fpga/gpmc/xilinx/common/logic_analyzer_data_storage.v | |
| parent | 13aee3afa9400efaca8d3521390bd74d65dd7c48 (diff) | |
| download | ulab-061289c61346568047e75a15f4ab1b874e4654d1.tar.gz ulab-061289c61346568047e75a15f4ab1b874e4654d1.zip | |
Max out logic analyzer memory
Diffstat (limited to 'fpga/gpmc/xilinx/common/logic_analyzer_data_storage.v')
| -rw-r--r-- | fpga/gpmc/xilinx/common/logic_analyzer_data_storage.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/fpga/gpmc/xilinx/common/logic_analyzer_data_storage.v b/fpga/gpmc/xilinx/common/logic_analyzer_data_storage.v index c5cae3c..1dd957e 100644 --- a/fpga/gpmc/xilinx/common/logic_analyzer_data_storage.v +++ b/fpga/gpmc/xilinx/common/logic_analyzer_data_storage.v @@ -11,8 +11,8 @@ module logic_analyzer_data_storage( input clkb, input [63:0] dina, input [63:0] dinb, - input [8:0] addra, - input [8:0] addrb, + input [10:0] addra, + input [10:0] addrb, input wea, input web, output reg [63:0] douta, @@ -23,7 +23,7 @@ module logic_analyzer_data_storage( // Xilinx specific directive (* RAM_STYLE="BLOCK" *) - reg [RAM_WIDTH-1:0] data_storage_ram [(2**9)-1:0]; + reg [RAM_WIDTH-1:0] data_storage_ram [(2**11)-1:0]; always @(posedge clka) begin douta <= data_storage_ram[addra]; |