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authorTimothy Pearson <kb9vqf@pearsoncomputing.net>2014-01-12 15:59:45 -0600
committerTimothy Pearson <kb9vqf@pearsoncomputing.net>2014-01-12 15:59:45 -0600
commit061289c61346568047e75a15f4ab1b874e4654d1 (patch)
tree5b6e5fc0e84bf365f0735178680796ebc2593567 /fpga/gpmc/xilinx/common
parent13aee3afa9400efaca8d3521390bd74d65dd7c48 (diff)
downloadulab-061289c61346568047e75a15f4ab1b874e4654d1.tar.gz
ulab-061289c61346568047e75a15f4ab1b874e4654d1.zip
Max out logic analyzer memory
Diffstat (limited to 'fpga/gpmc/xilinx/common')
-rw-r--r--fpga/gpmc/xilinx/common/logic_analyzer_data_storage.v6
-rw-r--r--fpga/gpmc/xilinx/common/main.v26
2 files changed, 18 insertions, 14 deletions
diff --git a/fpga/gpmc/xilinx/common/logic_analyzer_data_storage.v b/fpga/gpmc/xilinx/common/logic_analyzer_data_storage.v
index c5cae3c..1dd957e 100644
--- a/fpga/gpmc/xilinx/common/logic_analyzer_data_storage.v
+++ b/fpga/gpmc/xilinx/common/logic_analyzer_data_storage.v
@@ -11,8 +11,8 @@ module logic_analyzer_data_storage(
input clkb,
input [63:0] dina,
input [63:0] dinb,
- input [8:0] addra,
- input [8:0] addrb,
+ input [10:0] addra,
+ input [10:0] addrb,
input wea,
input web,
output reg [63:0] douta,
@@ -23,7 +23,7 @@ module logic_analyzer_data_storage(
// Xilinx specific directive
(* RAM_STYLE="BLOCK" *)
- reg [RAM_WIDTH-1:0] data_storage_ram [(2**9)-1:0];
+ reg [RAM_WIDTH-1:0] data_storage_ram [(2**11)-1:0];
always @(posedge clka) begin
douta <= data_storage_ram[addra];
diff --git a/fpga/gpmc/xilinx/common/main.v b/fpga/gpmc/xilinx/common/main.v
index 6d8c743..a59c3ed 100644
--- a/fpga/gpmc/xilinx/common/main.v
+++ b/fpga/gpmc/xilinx/common/main.v
@@ -40,6 +40,7 @@ module main(
output reg userproc_start,
input userproc_done,
output reg userlogic_reset,
+ input userlogic_clock,
input [3:0] four_bit_leds,
input [7:0] eight_bit_leds,
@@ -114,19 +115,22 @@ module main(
.wea(lcd_data_storage_wea), .web(lcd_data_storage_web),
.douta(lcd_data_storage_douta), .doutb(lcd_data_storage_doutb));
+ wire logic_analyzer_clk;
+ logic_analyzer_clock_generator logic_analyzer_clock_generator(.clkin(clk), .clkout(logic_analyzer_clk));
+
wire logic_analyzer_data_storage_clka;
wire logic_analyzer_data_storage_clkb;
reg [63:0] logic_analyzer_data_storage_dina;
reg [63:0] logic_analyzer_data_storage_dinb;
- reg [8:0] logic_analyzer_data_storage_addra;
- reg [8:0] logic_analyzer_data_storage_addrb;
+ reg [10:0] logic_analyzer_data_storage_addra;
+ reg [10:0] logic_analyzer_data_storage_addrb;
reg logic_analyzer_data_storage_wea;
reg logic_analyzer_data_storage_web;
wire [63:0] logic_analyzer_data_storage_douta;
wire [63:0] logic_analyzer_data_storage_doutb;
assign logic_analyzer_data_storage_clka = clk;
- assign logic_analyzer_data_storage_clkb = clk;
+ assign logic_analyzer_data_storage_clkb = logic_analyzer_clk;
logic_analyzer_data_storage logic_analyzer_data_storage(.clka(logic_analyzer_data_storage_clka), .clkb(logic_analyzer_data_storage_clkb),
.dina(logic_analyzer_data_storage_dina), .dinb(logic_analyzer_data_storage_dinb),
@@ -243,8 +247,8 @@ module main(
reg logic_analyzer_trigger;
reg logic_analyzer_trigger_prev;
- reg [9:0] logic_analyzer_address_counter;
- always @(posedge clk) begin
+ reg [11:0] logic_analyzer_address_counter;
+ always @(posedge logic_analyzer_clk) begin
// Trigger
logic_analyzer_trigger = ~userlogic_reset; // Trigger on userlogic_reset falling edge
if ((logic_analyzer_trigger == 1) && (logic_analyzer_trigger_prev == 0)) begin
@@ -252,7 +256,7 @@ module main(
end
// Data load
- if (logic_analyzer_address_counter < 9'b100000000) begin
+ if (logic_analyzer_address_counter[11] == 1'b0) begin
logic_analyzer_data_storage_addrb = logic_analyzer_address_counter;
// Connect signals to logic analyzer
@@ -266,8 +270,8 @@ module main(
logic_analyzer_data_storage_dinb[59:44] = usermem_address;
logic_analyzer_data_storage_dinb[60] = usermem_wen;
logic_analyzer_data_storage_dinb[61] = usermem_wait;
- logic_analyzer_data_storage_dinb[62] = 1'b0;
- logic_analyzer_data_storage_dinb[63] = 1'b0;
+ logic_analyzer_data_storage_dinb[62] = 1'b0; // UNUSED
+ logic_analyzer_data_storage_dinb[63] = userlogic_clock;
logic_analyzer_data_storage_web = 1'b1;
logic_analyzer_address_counter = logic_analyzer_address_counter + 1;
@@ -383,7 +387,7 @@ module main(
// 0x0c: User device control
// Bit 0: User logic reset
// 0x20 - 0x3f: LCD data area
- // 0x1000 - 0x1fff: Logic analyzer data area (read only)
+ // 0x4000 - 0x7fff: Logic analyzer data area (read only)
if (gpmc_wen_reg == 1'b0) begin
if (gpmc_address_reg[(RAM_ADDR_BITS-1):5] == 1) begin // Address range 0x20 - 0x3f
lcd_data_storage_addra = gpmc_address_reg[4:0];
@@ -419,8 +423,8 @@ module main(
lcd_data_storage_addra = gpmc_address_reg[4:0];
lcd_data_storage_wea = 1'b0;
gpmc_data_out = lcd_data_storage_douta;
- end else if (gpmc_address_reg[(RAM_ADDR_BITS-1):12] == 1) begin // Address range 0x1000 - 0x1fff
- logic_analyzer_data_storage_addra = gpmc_address_reg[12:3];
+ end else if (gpmc_address_reg[(RAM_ADDR_BITS-1):14] == 1) begin // Address range 0x4000 - 0x7fff
+ logic_analyzer_data_storage_addra = gpmc_address_reg[13:3];
logic_analyzer_data_storage_wea = 1'b0;
case (gpmc_address_reg[2:0])
0: begin