ulab - Donated space for related uLab project

	Commit message (Collapse)	Author	Age	Files	Lines
*	First pass of logic analyzer functionality (client and FPGA core)	Timothy Pearson	2014-02-27	14	-224/+846
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*	Add ability to hard reset user device	Timothy Pearson	2014-01-13	2	-1/+10
\| \| \| \|	Fix initial size of serial and terminal windows
*	Add serial I/O to host FPGA	Timothy Pearson	2014-01-12	2	-0/+13
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*	Max out logic analyzer memory	Timothy Pearson	2014-01-12	5	-17/+102
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*	Add logic analyzer block to control FPGA	Timothy Pearson	2014-01-11	4	-6/+149
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*	Relayout the GUI to be more in line with expected norms	Timothy Pearson	2014-01-10	3	-113/+131
\| \| \| \| \|	Add user logic reset signal Stabilize data transfer
*	Increase DSP memory size	Timothy Pearson	2014-01-10	2	-1/+7
\| \| \| \|	Fix potential crash in FPGA viewer if hardware debug interface is malfunctioning or offline
*	Move hardware design files to their correct locations	Timothy Pearson	2014-01-09	7	-510/+474
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*	Add initial GOMC compatible uLab debug system hardware design files	Timothy Pearson	2014-01-09	5	-0/+1007