| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add a several cycle "dead zone" to 7-segment decoder segment select lines to ↵ | Timothy Pearson | 2019-04-28 | 1 | -16/+55 |
| | | | | | more accurately emulate real hardware | ||||
| * | Correctly implement 7-segment display LED persistence | Timothy Pearson | 2019-04-28 | 1 | -12/+16 |
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| * | Add user logic reset support to serial version of FPGA control interface | Timothy Pearson | 2019-04-28 | 1 | -0/+12 |
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| * | Add intial version of Lattice remote FPGA interface | Timothy Pearson | 2019-04-28 | 1 | -1/+30 |
| | | | | | Minor tweaks to core remote FPGA file to eliminate Yosys warnings and reduce design size | ||||
| * | Modify FPGA interface license to AGPL v3 | Timothy Pearson | 2019-04-28 | 1 | -2/+5 |
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| * | Add initial GOMC compatible uLab debug system hardware design files | Timothy Pearson | 2014-01-09 | 1 | -0/+1253 |
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index : ulab | |
| Donated space for related uLab project | TDE Gitea Workspace |
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