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* Relayout the GUI to be more in line with expected normsTimothy Pearson2014-01-101-1/+1
| | | | | Add user logic reset signal Stabilize data transfer
* Add initial GOMC compatible uLab debug system hardware design filesTimothy Pearson2014-01-098-741/+0
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* Add initial GPMC test program and associated files for BeagleBone BlackTimothy Pearson2014-01-092-2/+3
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* Add initial version of SVF player for Beaglebone BlackTimothy Pearson2014-01-014-0/+593
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* Fix prior commitTimothy Pearson2013-10-301-1/+1
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* Fix progress bar not moving during DSP data receptionTimothy Pearson2013-10-301-4/+6
| | | | Fix syntax error in demo main.v file
* Allow data processing RAM size to be configured by changing a Verilog ↵Timothy Pearson2013-10-302-10/+12
| | | | parameter on the FPGA side
* Fix image distortion when certain greyscale values are utilizedTimothy Pearson2013-10-301-12/+12
| | | | Store last used values in FPGA viewer and programmer GUI for convenience on GUI restart
* Fix 7-segment LED display and add sample driver for the sameTimothy Pearson2013-10-142-12/+67
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* Use 10-pin headers for ulab debug interface serial port on Spartan 6Timothy Pearson2013-04-211-2/+2
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* Add sample image processing module to Spartan 6 demo projectTimothy Pearson2013-04-171-5/+72
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* Properly report device programming errorsTimothy Pearson2013-04-151-0/+11
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* Avoid usage of TQTimer::singleShot in the FPGA viewer partTimothy Pearson2013-03-131-1/+1
| | | | Repair "think-o" in the Spartan 6 block RAM HDL
* Add sample design for Spartan 6 and ISE 14.4Timothy Pearson2013-03-138-3/+615
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* Update remote debug module and clean up FPGA section of the source treeTimothy Pearson2013-03-133-2364/+3
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* Add verified Xilinx programming script and device type extractorTimothy Pearson2012-11-203-1/+107
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* Minor cleanupTimothy Pearson2012-11-201-10/+11
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* Add magic 64 bytes to S6 svf fileTimothy Pearson2012-11-202-2/+27
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* Add initial untested support for Spartan 6 devicesTimothy Pearson2012-11-202-1/+84
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* Initial rpi jtag supportTimothy Pearson2012-10-041-106/+93
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* Update makefilesTimothy Pearson2012-10-022-4/+58
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* Add initial files for direct FPGA programmingTimothy Pearson2012-10-0196-0/+26114
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* Add public domain FPGA files for Xilinx s3/s3eTimothy Pearson2012-05-142-0/+2364