From 061289c61346568047e75a15f4ab1b874e4654d1 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sun, 12 Jan 2014 15:59:45 -0600 Subject: Max out logic analyzer memory --- fpga/gpmc/xilinx/common/logic_analyzer_data_storage.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'fpga/gpmc/xilinx/common/logic_analyzer_data_storage.v') diff --git a/fpga/gpmc/xilinx/common/logic_analyzer_data_storage.v b/fpga/gpmc/xilinx/common/logic_analyzer_data_storage.v index c5cae3c..1dd957e 100644 --- a/fpga/gpmc/xilinx/common/logic_analyzer_data_storage.v +++ b/fpga/gpmc/xilinx/common/logic_analyzer_data_storage.v @@ -11,8 +11,8 @@ module logic_analyzer_data_storage( input clkb, input [63:0] dina, input [63:0] dinb, - input [8:0] addra, - input [8:0] addrb, + input [10:0] addra, + input [10:0] addrb, input wea, input web, output reg [63:0] douta, @@ -23,7 +23,7 @@ module logic_analyzer_data_storage( // Xilinx specific directive (* RAM_STYLE="BLOCK" *) - reg [RAM_WIDTH-1:0] data_storage_ram [(2**9)-1:0]; + reg [RAM_WIDTH-1:0] data_storage_ram [(2**11)-1:0]; always @(posedge clka) begin douta <= data_storage_ram[addra]; -- cgit v1.2.1