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| author | Timothy Pearson <kb9vqf@pearsoncomputing.net> | 2013-10-30 13:12:43 -0500 |
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| committer | Timothy Pearson <kb9vqf@pearsoncomputing.net> | 2013-10-30 13:12:43 -0500 |
| commit | f27e0f01840bcc42e521beb29b4f5964b1649bda (patch) | |
| tree | 01011ca0cc9b0c5f66d3e6c4e1e1410220065cc8 /attic | |
| parent | 8faa3da1094d1785d3343c2869d9f8c95f01cf97 (diff) | |
| download | ulab-f27e0f01840bcc42e521beb29b4f5964b1649bda.tar.gz ulab-f27e0f01840bcc42e521beb29b4f5964b1649bda.zip | |
Allow data processing RAM size to be configured by changing a Verilog parameter on the FPGA side
Diffstat (limited to 'attic')
0 files changed, 0 insertions, 0 deletions