First pass of logic analyzer functionality (client and FPGA core)

1 files changed, 22 insertions, 6 deletions

diff --git a/fpga/gpmc/xilinx/common/lcd_data_storage.v b/fpga/gpmc/xilinx/common/lcd_data_storage.v
index c1f3559..8f7adac 100644
--- a/fpga/gpmc/xilinx/common/lcd_data_storage.v
+++ b/fpga/gpmc/xilinx/common/lcd_data_storage.v
@@ -23,22 +23,38 @@ module lcd_data_storage(
 	// Xilinx specific directive
 	(* RAM_STYLE="BLOCK" *)
 	
-	reg [RAM_WIDTH-1:0] data_storage_ram [(2**5)-1:0];
-	
+	reg [RAM_WIDTH-1:0] lcd_data_storage_ram [(2**5)-1:0];
+
+	// Registered
 	always @(posedge clka) begin
-		douta <= data_storage_ram[addra];
+		douta <= lcd_data_storage_ram[addra];
 		if (wea) begin
-			data_storage_ram[addra] <= dina;
+			lcd_data_storage_ram[addra] <= dina;
 			douta <= dina;
 		end
 	end
 
 	always @(posedge clkb) begin
-		doutb <= data_storage_ram[addrb];
+		doutb <= lcd_data_storage_ram[addrb];
 		if (web) begin
-			data_storage_ram[addrb] <= dinb;
+			lcd_data_storage_ram[addrb] <= dinb;
 			doutb <= dinb;
 		end
 	end
 
+// 	// Unregistered
+// 	always @(posedge clka) begin
+// 		if (wea) begin
+// 			lcd_data_storage_ram[addra] <= dina;
+// 		end
+// 	end
+// 	assign douta = lcd_data_storage_ram[addra];
+// 
+// 	always @(posedge clkb) begin
+// 		if (web) begin
+// 			lcd_data_storage_ram[addrb] <= dinb;
+// 		end
+// 	end
+// 	assign doutb = lcd_data_storage_ram[addrb];
+
 endmodule