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author | Timothy Pearson <kb9vqf@pearsoncomputing.net> | 2012-10-01 21:07:55 -0500 |
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committer | Timothy Pearson <kb9vqf@pearsoncomputing.net> | 2012-10-01 21:07:55 -0500 |
commit | d1b70f80180fe4b5ac6078e2be9678fc36d74c5c (patch) | |
tree | 2e46de7a644f89e36842247af6826ff00a0d3fa4 /fpga/xilinx/programmer/bit2svf/usage.txt | |
parent | ae161b4a6a978922747cf09e8c04479340825852 (diff) | |
download | ulab-d1b70f80180fe4b5ac6078e2be9678fc36d74c5c.tar.gz ulab-d1b70f80180fe4b5ac6078e2be9678fc36d74c5c.zip |
Add initial files for direct FPGA programming
Diffstat (limited to 'fpga/xilinx/programmer/bit2svf/usage.txt')
-rw-r--r-- | fpga/xilinx/programmer/bit2svf/usage.txt | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/fpga/xilinx/programmer/bit2svf/usage.txt b/fpga/xilinx/programmer/bit2svf/usage.txt new file mode 100644 index 0000000..f04266d --- /dev/null +++ b/fpga/xilinx/programmer/bit2svf/usage.txt @@ -0,0 +1,63 @@ +Copyright (c) 2005 Juan Pablo D. Borgna <jpborgna en inti gov ar> +Copyright (c) 2005 Instituto Nacional de Tecnología Industrial +Copyright (c) 2001, 2002 by David Sullins +Licese: GPL por bitfile.c + + +jbit: +----- + This script is a shortcut for programming a device using the GNU JTAG + program with a .bit file. It generates and deletes the intermediate SVF + file. It can read a personal config, refer to jbitrc_sample.txt. + +Sample: + +bit2svf$ ./jbit ejemplo_prom.bit XC18V01 + +jbit - bit2svf/jtag short cut - v1.0 +Copyright (c) 2005 Juan Pablo D. Borgna/INTI + +Creando archivo temporario /tmp/bit2svf.tmp + +bit2svf - SVF file generator - v1.0 +Copyright (c) 2005 Juan Pablo D. Borgna/INTI + + +Bit file created on 2004/08/25 at 13:43:18. +Created from file ejemplo.ncd for Xilinx part 2s100pq208. +Bitstream length is 97652 bytes. + +Process finsished sucefully. +Creado ok +Invocando /home/jpablo/usr/bin/jtag +Initializing Xilinx DLC5 JTAG Parallel Cable III on ppdev port /dev/parport0 +IR length: 8 +Chain length: 1 +Device Id: 00000101000000100100000010010011 + Manufacturer: Xilinx + Part: XC18V01-SO20 + Stepping: 1 + Filename: /home/jpablo/usr//share/jtag/xilinx/xc18v01-so20/xc18v01-so20 +Warning svf: checking of TDO not supported for SIR. + This message is only displayed once. +Borrando temporarios.. +Que tenga un buen dia :-) + + + +bit2svf: +-------- + This program generates a SVF file wich using the program JTAG it is + possible to program a FPGA or PROM. + +Sample: + +bit2svf$ ./bit2svf ejemplo_prom.bit ejemplo_prom.svf XC18V01 + +Bit file created on 2004/08/25 at 13:43:18. +Created from file ejemplo.ncd for Xilinx part 2s100pq208. +Bitstream length is 97652 bytes. + +Process finsished sucefully. + + |