| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix prior commit | Timothy Pearson | 2013-10-30 | 1 | -3/+3 |
| * | Allow data processing RAM size to be configured by changing a Verilog paramet... | Timothy Pearson | 2013-10-30 | 1 | -13/+40 |
| * | Fix image distortion when certain greyscale values are utilized | Timothy Pearson | 2013-10-30 | 1 | -148/+145 |
| * | Fix 7 segment display malfunction at low multiplexing rates | Timothy Pearson | 2013-10-15 | 1 | -8/+8 |
| * | Fix 7-segment LED display and add sample driver for the same | Timothy Pearson | 2013-10-14 | 1 | -21/+50 |
| * | Update remote debug module and clean up FPGA section of the source tree | Timothy Pearson | 2013-03-13 | 1 | -0/+1200 |
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