| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | First pass of logic analyzer functionality (GPMC interface and server) | Timothy Pearson | 2014-02-27 | 1 | -1/+25 |
| | | |||||
| * | Hard reset user device on connection and disconnection of FPGA viewer | Timothy Pearson | 2014-01-13 | 1 | -1/+3 |
| | | |||||
| * | Add initial version of a logic analyzer server | Timothy Pearson | 2014-01-12 | 1 | -3/+14 |
| | | |||||
| * | Lower the uLab FPGA viewer GPMC clock to reduce errors on prototype lashup | Timothy Pearson | 2014-01-10 | 1 | -5/+122 |
| | | | | | Add memory stress tests to GPMC test program | ||||
| * | Add initial GPMC test program and associated files for BeagleBone Black | Timothy Pearson | 2014-01-09 | 4 | -0/+442 |
 |
index : ulab | |
| Donated space for related uLab project | TDE Gitea Workspace |
| summaryrefslogtreecommitdiffstats |