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* Fix progress bar not moving during DSP data receptionTimothy Pearson2013-10-301-4/+6
* Allow data processing RAM size to be configured by changing a Verilog paramet...Timothy Pearson2013-10-302-10/+12
* Fix image distortion when certain greyscale values are utilizedTimothy Pearson2013-10-301-12/+12
* Fix 7-segment LED display and add sample driver for the sameTimothy Pearson2013-10-142-12/+67
* Use 10-pin headers for ulab debug interface serial port on Spartan 6Timothy Pearson2013-04-211-2/+2
* Add sample image processing module to Spartan 6 demo projectTimothy Pearson2013-04-171-5/+72
* Avoid usage of TQTimer::singleShot in the FPGA viewer partTimothy Pearson2013-03-131-1/+1
* Add sample design for Spartan 6 and ISE 14.4Timothy Pearson2013-03-138-3/+615
* Update remote debug module and clean up FPGA section of the source treeTimothy Pearson2013-03-133-2364/+3
* Add public domain FPGA files for Xilinx s3/s3eTimothy Pearson2012-05-142-0/+2364