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* Add test program for Lattice guest FPGAsTimothy Pearson2019-04-283-0/+333
* Add user logic reset support to serial version of FPGA control interfaceTimothy Pearson2019-04-283-1/+17
* Add intial version of Lattice remote FPGA interfaceTimothy Pearson2019-04-289-1/+350
* Modify FPGA interface license to AGPL v3Timothy Pearson2019-04-281-2/+5
* Update copyright datesTimothy Pearson2019-01-241-1/+1
* First pass of logic analyzer functionality (GPMC interface and server)Timothy Pearson2014-02-271-1/+25
* First pass of logic analyzer functionality (client and FPGA core)Timothy Pearson2014-02-2714-224/+846
* Add ability to hard reset user deviceTimothy Pearson2014-01-132-1/+10
* Hard reset user device on connection and disconnection of FPGA viewerTimothy Pearson2014-01-131-1/+3
* Add serial I/O to host FPGATimothy Pearson2014-01-122-0/+13
* Add initial version of a logic analyzer serverTimothy Pearson2014-01-121-3/+14
* Max out logic analyzer memoryTimothy Pearson2014-01-125-17/+102
* Merge branch 'master' of http://scm.trinitydesktop.org/scm/git/remotelaboratoryTimothy Pearson2014-01-111-5/+122
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| * Lower the uLab FPGA viewer GPMC clock to reduce errors on prototype lashupTimothy Pearson2014-01-101-5/+122
* | Add logic analyzer block to control FPGATimothy Pearson2014-01-114-6/+149
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* Relayout the GUI to be more in line with expected normsTimothy Pearson2014-01-104-114/+132
* Increase DSP memory sizeTimothy Pearson2014-01-102-1/+7
* Move hardware design files to their correct locationsTimothy Pearson2014-01-097-510/+474
* Add initial GOMC compatible uLab debug system hardware design filesTimothy Pearson2014-01-0914-0/+1007
* Add initial GPMC test program and associated files for BeagleBone BlackTimothy Pearson2014-01-096-2/+445
* Add initial version of SVF player for Beaglebone BlackTimothy Pearson2014-01-014-0/+593
* Fix prior commitTimothy Pearson2013-10-301-1/+1
* Fix progress bar not moving during DSP data receptionTimothy Pearson2013-10-301-4/+6
* Fix prior commitTimothy Pearson2013-10-301-3/+3
* Allow data processing RAM size to be configured by changing a Verilog paramet...Timothy Pearson2013-10-303-23/+52
* Fix image distortion when certain greyscale values are utilizedTimothy Pearson2013-10-302-160/+157
* Fix 7 segment display malfunction at low multiplexing ratesTimothy Pearson2013-10-151-8/+8
* Fix 7-segment LED display and add sample driver for the sameTimothy Pearson2013-10-143-33/+117
* Use 10-pin headers for ulab debug interface serial port on Spartan 6Timothy Pearson2013-04-211-2/+2
* Add sample image processing module to Spartan 6 demo projectTimothy Pearson2013-04-171-5/+72
* Properly report device programming errorsTimothy Pearson2013-04-151-0/+11
* Avoid usage of TQTimer::singleShot in the FPGA viewer partTimothy Pearson2013-03-131-1/+1
* Add sample design for Spartan 6 and ISE 14.4Timothy Pearson2013-03-138-3/+615
* Update remote debug module and clean up FPGA section of the source treeTimothy Pearson2013-03-134-2364/+1203
* Add verified Xilinx programming script and device type extractorTimothy Pearson2012-11-203-1/+107
* Minor cleanupTimothy Pearson2012-11-201-10/+11
* Add magic 64 bytes to S6 svf fileTimothy Pearson2012-11-202-2/+27
* Add initial untested support for Spartan 6 devicesTimothy Pearson2012-11-202-1/+84
* Initial rpi jtag supportTimothy Pearson2012-10-041-106/+93
* Update makefilesTimothy Pearson2012-10-022-4/+58
* Add initial files for direct FPGA programmingTimothy Pearson2012-10-0196-0/+26114
* Add public domain FPGA files for Xilinx s3/s3eTimothy Pearson2012-05-142-0/+2364
generated by cgit v1.2.1 (git 2.18.0) at 2024-12-27 02:22:29 +0000